1. Field of the Invention
The present invention relates to an apparatus for converting data when the data is to be recorded at high density on a recording medium or to be transmitted by a band-limited transmission system.
2. Description of the Related Art
In general, to record data, expressed in binary codes, on a recording medium at high density or transmit such data to a transmission system, the data needs to be converted to have a signal waveform suitable for high-density processing before recording or transmission. More specifically, data conversion is conducted such that, with respect to the signal waveform after the conversion, the minimum inversion period (hereinafter indicated by Tmin) is long while the maximum inversion period (hereinafter indicated by Tmax) is short. This is because longer Tmin reduces interference of adjacent inversions to thereby ensure high-density processing and shorter Tmax facilitates self-synchronization of clocks. Further, a transmission system, which does not transfer DC components, deforms the waveform of a signal to be transferred if the signal includes a DC component. It is therefore desirable that the data conversion eliminate the DC component.
An example of the data converting system, which satisfies these conditions, is disclosed in Japanese Unexamined Patent Publication No. 75353/1983. This system will be described below.
A train or series of input data is divided into consecutive 2-bit blocks as shown in (A) in FIG. 1. These blocks will be sequentially labeled B.sub.1, B.sub.2, B.sub.3, B.sub.4, ..., B.sub.7 from the foremost block. The 2-bit binary codes of blocks other than every pair of adjoining blocks whose bits before and after the adjoining point are both "1" like those bits of B.sub.4 and B.sub.5, are sequentially converted into 3-bit binary codes in accordance with, for example, a conversion table as presented in Table 2. The 2-bit binary codes of those adjoining two blocks, like B.sub.4 and B.sub.5, whose bits before and after the adjoining point are both "1," are converted into 3-bit binary codes according to a conversion table as presented in Table 2. Sequential conversion from the foremost block can yield a series of codes as shown in (B) in FIG. 1, wherein the minimum and maximum numbers of "0"s present between the adjoining "1"s are one and seven, respectively. With "1" associated with inversion and "0" with non-inversion, Tmin takes a large value of 4/3.multidot.T while Tmax takes a value of 16/3.multidot.T where T is the bit interval before the conversion, thus ensuring self-synchronization.
After the above conversion, the second conversion is to be further carried out to eliminate a DC component. More specifically, the 3-bit binary codes of every l blocks are converted into 4-bit binary codes in accordance with a conversion table, such as Table 3, thus yielding a code series as shown in (C) in FIG. 1 wherein l=6. Table 3 shows three types of 3-bit binary-code patterns to each of which two types of 4-bit patterns P.sub.1 and P.sub.2 are assigned. These 3-bit patterns will be converted into either P.sub.1 or P.sub.2, whichever desirable to reduce the DC component of a final signal waveform after conversion. That is, either P.sub.1 or P.sub.2 is selected to make the absolute value of a DSV (Digital Sum Value) smaller; the DSV is the accumulated sum of values "+1" assigned to the level "1" of the signal waveform, and "-1" assigned to the level "0" of that waveform. For instance, with the DSV being "0" at a point a in (C) in FIG. 1, the DSV at a point b is "-1". The first block in (C) in FIG. 1 is converted into "1000" because if it were converted into "1010", the DSV at the point b would become "+5." The three 4-bit patterns, "0000", "0001" and "1000" are selectable only when Tmax is not greater than 16/3.multidot.T, namely when "0" does not appear eight times or more consecutively. If the conversion shown in Table 3 is effected for every l blocks, Tmin and Tmax will be expressed as follows through the data conversion given in Tables 1 to 3. ##EQU1## This data conversion system realizes longer Tmax and shorter Tmax as well as the elimination of the DC component in the above manner. Since this system performs the second conversion every l blocks, however, it needs a buffer memory having a capacity of 3l+1 bits or greater to average the data rate of the output code series. This complicates the circuit configuration. In addition, it is necessary to prevent Tmax from exceeding its limit at the time of selecting the 4-bit pattern. The selection may not always be so made as to set the DSV small. The value for l therefore cannot be set very large, thus increasing the redundancy originating from the second conversion to eliminate the DC component.
TABLE 1 ______________________________________ Input Data After Conversion ______________________________________ 00 010 01 001 10 100 11 101 ______________________________________
TABLE 2 ______________________________________ Input Data After Conversion ______________________________________ 01 .multidot. 10 010 .multidot. 000 01 .multidot. 11 001 .multidot. 000 11 .multidot. 10 100 .multidot. 000 11 .multidot. 11 101 .multidot. 000 ______________________________________
TABLE 3 ______________________________________ Data in FIG. 1(B) After Conversion ______________________________________ 010 P.sub.1 0010 P.sub.2 0000 001 P.sub.1 0101 P.sub.2 0001 100 P.sub.1 1010 P.sub.2 1000 000 P.sub.1 0100 101 P.sub.2 0000 ______________________________________
A description will now be given of another DC component eliminating system as disclosed, for example, Japanese Examined Patent Publication No. 27510/1989. According to this system, input binary data is converted into a code-converted bit series so as to provide the desired Tmin and Tmax, then this bit series is divided into N-bit blocks (N=integer), and a redundancy bit consisting of M bits (M=integer) is inserted between consecutive two blocks. Then, DSV control is executed to eliminate the DC by the value of the redundancy bit within the range to meet the limit of Tmin. That is, this system inserts a redundancy bit to eliminate the DC component in place of the second conversion done in the previously-described system. It is however necessary to control the DSV without breaking the limit of Tmin by the redundancy bit. Therefore, if the number of the redundancy bits, M, is set small, the degree of freedom will result in insufficient DSV control. With regard to Tmax, no specific measure is taken against Tmax exceeding its limit. If one tries to set Tmax within the limit, however, the degree of freedom will further diminish. To realize sufficient DSV control, therefore, M cannot be set so small while N cannot be set so large. This restriction inevitably increases the redundancy to eliminate the DC component.